Koppar

Reliability

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How to connect

Add it to any MCP client that supports remote servers.

{
  "mcpServers": {
    "koppar": {
      "type": "http",
      "url": "https://app.koppar.ai/mcp"
    }
  }
}

65 tools

• get_workflow_guide

  How to drive Koppar end to end, and the instructions for each stage you do yourself: "research" (part research and the dossier), "synthesis" (writing the SKiDL schematic), "review" (design review), "board" (the board plan). Read the stage guide before doing that stage.

• create_design

  Start a new design from the user's brief (what the board must do, its interfaces, power, size and constraints). Returns the design_id every other tool takes and the web_url where the user follows the design. Uses no generation quota: the work is done by you.

• list_designs

  The user's designs, newest first, including ones made in the web app (an agent can continue those too) and board workspaces (kind "board workspace"). With trashed, the designs in the trash instead (deleted, restorable for 7 days).

• delete_design

  Move a design (or a board workspace) to the trash: it leaves list_designs and the web app, and restore_design brings it back for 7 days, after which it is removed for good. permanent removes it, its files and its session right away. Refused while a run on it is in progress. The…

• restore_design

  Put a deleted design back from the trash (within 7 days of delete_design).

• get_design

  Where a design stands: the brief, the schematic (accepted or the last blocking error, ERC, part and net counts, submissions), the board run, the readable files, and the next step.

• search_kicad_symbol

  Search KiCad's standard symbol libraries for parts whose name contains a substring. Use this whenever you are not 100% sure the (library, name) pair you're about to pass to Part(...) exists. Always prefer the package-suffixed variant the search returns over a generic name. If a…

• get_kicad_symbol

  Return the full pin list (number, name, electrical type) and description for a specific KiCad symbol. For some high-risk power parts it also returns curated topology_constraints from datasheet-style application notes and footprint_suggestions. Use this before writing pin…

• search_kicad_footprint

  Search KiCad's standard footprint libraries. Returns 'Library:Footprint' strings suitable for the footprint= argument of Part(...). Query with the package family and pin count ('LGA-14', 'QFN-24', 'SOIC-8'), optionally a body size or pitch. When no name contains every word…

• create_custom_symbol

  Register a connectable schematic symbol for a part that is NOT in KiCad's libraries (search_kicad_symbol returned nothing). Use this for specialty ICs — LED-matrix drivers, niche sensors, etc. — INSTEAD of telling the synthesizer to model the part with discrete passives (which…

• add_custom_footprint

  Give the design a footprint of your own: a KiCad .kicad_mod (the file's text) for a package KiCad's libraries lack. It joins the design's "custom" footprint library and is used as "custom:<name>": pass that to create_custom_symbol (footprint=) or name it in the SKiDL script's…

• save_dossier

  Store the research dossier (markdown with ## Parts list, ## Power rails, ## Topology constraints, ## Notes, as the research guide describes). The verified pin tables from your lookups on this design are appended, and verified entries the design already had for parts you did not…

• submit_circuit

  Compile and check a complete SKiDL script: the symbol and footprint pre-flight (unambiguous typos are corrected and listed), SKiDL, the ERC score, KiCad ERC, floating subsystems, parts without a footprint, and supplier sourcing. Returns accepted plus blocking findings to fix and…

• edit_circuit

  Apply SEARCH/REPLACE patches to your latest script and re-run every check, as submit_circuit does. The latest script is your last submission when it was sent back (attempt_N_circuit.py), otherwise the design's circuit.py. Each search must match the current file exactly once…

• read_design_file

  Read a text file of the design: prompt.txt (brief), dossier.md, circuit.py, circuit.net, result.json, circuit.erc.json (KiCad ERC violations), attempt_N_circuit.py / attempt_N_error.txt, board_plan.json, pcb_result.json, pcb_run.log, circuit.drc.json (KiCad DRC)…

• get_review_packet

  Everything a design review needs in one text: the brief, the dossier, circuit.py and the compiled connectivity (every net with every pin and its function), with the reviewer instructions. Review it yourself and fix blockers with edit_circuit.

• get_board_context

  What the board plan is decided from: the computed minimum board, BOARD STATS (pad density, fine-pitch parts, fanout), the parts and nets, board instructions the user gave, and the plan schema with its rules. Needs an accepted schematic.

• start_board

  Start place and route with your board plan (the JSON object from the board guide: board, stated, edge, chain, groups, near, side, fixed, keepouts, netClasses). The plan is clamped and returned as applied. Runs for minutes in the background: follow it with get_board_status. Needs…

• get_board_status

  The board run: stage, size, layers, placement, routing completion, open nets, DRC counts; once finished, DRC violations by type, whether the fab files are released and, when not, the diagnosed causes (first = fix first: parts that did not fit, collisions, missing footprints…

• get_bom

  The live-priced BOM: each line with references, value, footprint, the chosen offer (seller, part number, MPN, price, stock, match quality), alternatives and totals. refresh asks the sellers again (tens of seconds).

• choose_bom_part

  Pick which offer a BOM line uses: the line's references and a seller part number or MPN from its offer or alternatives in get_bom; null goes back to the automatic pick. Sourcing only: a different component is a circuit change.

• consolidate_bom_basic

  Move every resistor, capacitor and inductor bought outside JLCPCB's basic library onto an in-stock basic-library part of the same value, package and (capacitors) at least the same voltage rating. Each part outside that library adds a loading fee to a JLCPCB order, usually more…

• get_fab_status

  Whether the board has earned its fab files (zero serious DRC errors, nothing unconnected), and if not, why not.

• list_order_providers

  The PCB and assembly providers, whether each can quote and take this kind of board today, and what a handoff sends them.

• get_order_price

  One price for a quantity: parts from the sellers, the board and assembly from the chosen provider's quote, setup fees, and what the total does not include.

• send_order_to_provider

  Upload the released board (Gerbers, BOM, placement) to a manufacturer and return the page where the user pays. This publishes the design to a third party: call it only when the user has explicitly asked to order from that provider, and set user_confirmed only then. Some…

• upload_board

  Replace the design's board with a .kicad_pcb you routed or edited yourself (the file, base64). The board must carry the design's circuit: every schematic part by reference, every pad on the net the netlist gives it; a footprint swap is allowed and recorded. Anything else is…

• get_downloads

  Download URLs for the design (KiCad project, schematic, netlist, BOM CSV, board file, 3D model, Gerbers, order bundle) and which are available now. They take the same Authorization: Bearer API key; the CLI fetches them with `koppar download <design> <artifact>`.

• import_kicad_project

  Bring an existing KiCad project in as a board workspace: the project folder as a ZIP (the .kicad_pcb, .kicad_pro, schematics, footprint and 3D-model folders), base64-encoded, up to about 18 MB zipped. The CLI does this with `koppar import <folder>`. Or from_design_id: the KiCad…

• get_board_info

  The board as it stands: copper layers, outline, design rules and net classes, counts (footprints, nets, tracks, vias, zones, keepouts, KiCad unconnected items), zones and keepouts, and every footprint with reference, value, footprint, position (origin, mm), rotation, side…

• place_footprints

  Put footprints exactly where given: KiCad board coordinates of the footprint origin in mm (y grows downward), rotation in degrees as KiCad shows it, side F or B (changing side flips the footprint, as KiCad does), locked. dx_mm/dy_mm/drot_deg move relative to where it is. Nothing…

• auto_place

  Pack footprints inside the board outline with Koppar's heuristic placer (ratsnest-driven, courtyard-legal). By default every unlocked footprint moves and locked ones stay; refs names exactly which move (all others stay). Constraints: fixed (exact origin positions and rotation…

• anneal_place

  Dense placement by simulated annealing: wirelength inside the outline with courtyard gaps, edge connectors held on their edge, fixed and locked parts held, keepout rectangles kept clear (routing corridors), and a per-pad price for the bottom side (flip_cost, mm of wirelength…

• set_board_outline

  Replace everything on Edge.Cuts with a new outline: rect (optionally with corner_radius_mm), a polygon of points, or fit_to_parts (the rectangle around every footprint courtyard plus margin_mm). Give exactly one.

• set_design_rules

  Set the project design rules (.kicad_pro) and copper layer count. Works on a board workspace and on a generated design (create_design → start_board). On a generated design the rules go into circuit.kicad_pro/.kicad_dru in place (the previous ones are snapshotted under…

• set_keepouts

  Add or remove keepout rule areas. Each keepout is a rect or polygon on the given copper layers (default all) and forbids what it names: no_tracks, no_vias, no_zone_fills (all three default true), no_pads, no_footprints. route_board keeps tracks and vias out of them and KiCad DRC…

• check_net_rules

  Check the copper against the project's net classes and differential pairs, which KiCad's DRC does not: every class or pair net's narrowest track and the length below its class width, and every pair (X_P/X_N, X+/X-, CAN X_H/X_L) with its coupled share at the class's…

• check_physics

  Judge the copper by physics, which KiCad's DRC does not: impedance from the stackup on controlled nets, IR drop and heating on rails with a stated current, pair and lane skew, a ground via beside every high-speed layer change, 3W spacing between high-speed runs, and the via path…

• set_zones

  Add or remove copper zones (pours). Each zone pours its net on the given copper layers over rect or polygon, by default the whole board outline. priority orders overlapping zones (higher fills first); clearance_mm and min_thickness_mm override the rules; thermal false connects…

• add_copper

  Lay exact copper by hand where the routers leave a gap: tracks as polylines on one copper layer, and through vias. width_mm, diameter_mm and drill_mm default to the board's current track and via sizes. Nets must exist on the board. Nothing is checked here: run_drc afterwards…

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